1. Field of the Invention
The present invention generally relates to quiescent current testing and, more particularly, to a system and method for detecting defects within a complementary metal oxide silicon (CMOS) circuit by measuring and characterizing the power supply current conducted by the circuit in multiple quiescent states.
2. Related Art
An ideal complementary metal oxide silicon (CMOS) integrated circuit conducts a negligible amount of current when the circuit is in standby or a quiescent state. Therefore, when a CMOS circuit is not switching states, only a small amount of quiescent current should be conducted by the circuit. The quiescent current, commonly referred to as xe2x80x9cIDDQ,xe2x80x9d is composed primarily of leakage current. A defective circuit may draw a significantly larger amount of quiescent current than a non-defective circuit.
Typical IDDQ testing includes setting a threshold value of IDDQ in which the circuit being tested is failed if the IDDQ conducted by the circuit exceeds the threshold value. In this regard, input vectors drive the circuit""s nodes to predetermined states, and the IDDQ is measured while the circuit""s nodes are held in the predetermined states. IDDQ testing may be done at a single state or it may include stepping through many different input test vectors to test various states. The test vectors can be generated by automatic test pattern generation (ATPG) software tools or by integrated circuit designers.
One of the difficulties of IDDQ testing is setting the threshold value. A circuit that draws more current than the threshold value of IDDQ for any input test vector is declared defective. A circuit that draws less current than the threshold value of IDDQ is considered non-defective. If the threshold value is set too high, then circuits that contain defects may be considered non-defective. If the threshold value is too low, then circuits that are free of defects may fail the IDDQ test. This increases the cost of the circuits considered non-defective. Therefore, the determination of the threshold value for IDDQ testing usually involves a tradeoff between the quality and the cost of the circuits which pass IDDQ testing.
As the scale of CMOS circuits is increasingly reduced to increase speed and density and to decrease cost, the background current drawn by the CMOS circuits is increased. As known in the art, IDDQ consists of two components (1) defect current, which is the current drawn by a circuit due to defects within the circuit and (2) background current, which is IDDQ minus the defect current. The scale of CMOS circuitry has reached levels where the magnitude of the background current is comparable to or even exceeds the defect current. Therefore, it has become more difficult to determine whether a variation in IDDQ is due to a variation in background current or is due to a defect, thereby frustrating the process of identifying which circuits are defective.
Process variations of the fabrication of electrical circuits further complicate the determination of the IDDQ threshold value. Process variations are differences that exist between individual circuits of the same circuit design. Process variations can affect the quiescent current drawn by the circuits. For example, two integrated circuits of the same design can draw different IDDQ values for the same set of input test vectors due to process variations between the two circuits.
Gattiker and Maly (A. E. Gattiker and W. Maly, xe2x80x9cCurrent Signaturesxe2x80x9d, Proc. VLSI Test Symposium, pp. 112-117, 1996) have proposed a method which eliminates some of the threshold selection problems. Traditionally, testing of a circuit ends as soon as the circuit fails the IDDQ test. Gattiker and Maly propose that IDDQ values be measured for a complete set of input test vectors. A complete set of input test vectors include enough test vectors to completely exercise the functionality of the circuitry within the circuit being tested. From the measured values of IDDQ, a current signature is generated. The current signature includes an ordering of the IDDQ measurements from the smallest value to the largest value. Gattiker and Maly claim that the magnitude of the measurements is not as important as the shape of a plot of the current signature. If there are no large jumps in the plot of the current signature, then the circuit is designated as non-defective. If the plot of the current signature includes any significant jumps or discontinuities, then the circuit is designated as defective.
The IDDQ signature concepts proposed by Gattiker and Maly represent important findings in IDDQ testing analysis. However, these concepts cannot be directly implemented into present-day integrated circuit manufacturing environments. Testing methods using the Gattiker and Maly IDDQ signature concepts require a complete set of input vector test settings to be applied to the integrated circuit under test and the resultant measured values of IDDQ for each input vector setting to be analyzed. Determination of the values of IDDQ for a complete set of input vector settings takes too long to implement in circuit manufacturing environment at a reasonable cost.
It is desirable to provide a system and method for IDDQ testing which overcomes the limitations of present IDDQ testing methods using a single threshold test. Furthermore, it is desirable that the method of IDDQ testing be easily implemented into existing circuit manufacturing environments by not requiring excessive storage and analysis of measured values of IDDQ.
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed herein. The present invention provides a system and method for detecting defects in electrical circuits by analyzing quiescent current.
In general, the present invention utilizes a circuit, a power supply unit, a current meter, and a analyzer. The power supply unit is connected to the circuit and transmits supply current to the circuit. The current meter measures the supply current and transmits a first signal and a second signal respectively indicating a first value and a second value of the supply current. The analyzer receives the first parameter and determines a threshold value based on the first parameter value. The analyzer then receives the second signal and compares the second signal to the threshold value. The analyzer determines whether a defect is detected based on the comparison of the second signal to the threshold value.
In accordance with another feature of the present invention, the analyzer also determines a second threshold value based on the first signal. The analyzer can then determine whether a defect is detected by comparing the second signal to the second threshold value.
In accordance with another feature of the present invention, the analyzer calculates the threshold values based on predetermined constants. To determine the predetermined constants, the values of signals indicating the supply current values for a plurality of states and a plurality of circuits are measured. Then, selected values of the signals are then plotted to create a current signature of the circuits. A regression is then used to remove outliers from the plot and to fit a curve or line to the plotted points. The predetermined constants are then determined from the fitted curve or line, and the predetermined constants are used by the analyzer to determine the threshold values for each of the circuits tested.
The present invention can also be viewed as providing a method for detecting defects within circuits. Briefly described, the method can be broadly conceptualized by the following steps: providing a circuit; measuring a value of a supply current associated with the circuit when the circuit is in a first state; determining a threshold value based on the value of the supply current measured in the measuring step; receiving a signal indicating another value of the supply current when the circuit is in a second state; comparing the signal to the threshold value; and detecting a defect in the circuit based on the comparing step.
The present invention has many advantages, a few of which are delineated hereafter, as mere examples.
An advantage of the present invention is that defects in circuits can be detected by comparing the quiescent current associated with circuit to threshold values. These comparisons can be achieved without determining the value of the quiescent current, thereby making the comparisons relatively fast.
Another advantage of the present invention is that the cost associated with quiescent current testing can be significantly reduced.
Another advantage of the present invention is that quiescent current testing can be achieved by comparing the quiescent current of a circuit to thresholds that are uniquely calculated for each circuit. Therefore, the effects of fluctuations in background current are reduced.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention, as is defined by the claims.